This invention is in the field of optical monitoring techniques, and relates to a method and system for monitoring a process of chemical mechanical planarization (CMP) applied to metal-based patterned articles. The invention is particularly useful in the manufacture of semiconductor devices.
In the manufacture of semiconductor devices, aluminum has been used almost exclusively as the main material for interconnects. However, recent developments in this field of the art have shown that copper is posed to take over as the main on-chip conductor for all types of integrated circuits. Compared to aluminum, copper has a lower resistance, namely less than 2 xcexcxcexa9-cm, even when deposited in narrow trenches, versus more than 3 xcexcxcexa9-cm for aluminum alloys. This lower resistance is critically important in high-performance microprocessors and fast static RAMs, since it enables signals to move faster by reducing the so-called xe2x80x9cResistance-Capacitancexe2x80x9d (RC) time delay. Additionally, copper has a superior resistance to electromigration, which leads to lower manufacturing costs as compared to aluminum-based structures.
During the manufacture of semiconductor devices, a wafer undergoes a sequence of photolithography-etching steps to produce a plurality of patterned layers (stacks). Then, depending on the specific layers or production process, the uppermost layer of the wafer may or may not undergo a CMP process to provide a smooth surface of this layer.
FIG. 1 illustrates the cross section of one possible example of a stack-like wafer structure 1 having aluminum interconnects. A silicon layer 2 serves as a substrate on which the stack is produced by sequentially depositing additional layers. A first layer 4 of silicon oxide, a so-called xe2x80x9cInterlayer Dielectric (ILD) insulating layerxe2x80x9d, is deposited on the substrate 2, and aluminum interconnects 6 are formed on the layer 4 by the deposition, photolithography and etching processes. Spaces between the interconnects 6 are filled with a further ILD layer 8. Tungsten (or other metal) vias 10 are produced above the aluminum interconnects 6 by the photolithography and deposition processes, and are aimed at connecting the lower aluminum layer 6 (line) with an upper one 12. The aluminum layer 12 is then patterned to form the required connections. Prior to depositing the upper aluminum layer 12, a CMP process is applied to the ILD layer 8 to flatten its upper surface. Hence, the upper aluminum layer 12 is almost smooth, and the only local topography existing therein is that caused by dimples 10A in the upper surface of the tungsten 10. As indicated above, all the spaces between the metal features are filled with the Silicon Oxide ILD layer 8 or other dielectric layers.
FIG. 2 illustrates a cross section of a stack-like wafer structure 20 utilizing copper interconnects patterned with a known dual Damascene process. The structure 20 includes a silicon layer (substrate) 22 (whose provision is optional), ILD layers 23A and 23B, and a patterned Silicon Nitride (SiN) layer 24. For a self-aligned via scheme, the SiN layer 24 should be patterned to form vias later on. Thereafter, an ILD layer 26 is deposited on top of the patterned SiN layer 24. Then, patterning (i.e., photolithography) and etching processes are applied to the layer 26 to form trenches therein. During the etching procedure, the layer 26 is removed up to SiN layer 24 within regions 28, while within regions 28A etching continues up to the layer 23B to form vias 29. Those manufacturers who do not use the SiN layer 24 have to conduct a more difficult two-step etching with two photolithography steps on a single thick silicone oxide layer. Further produced is a diffusion tantalum-based barrier layer 30 (or TiN or Ti), whose provision is aimed at preventing copper migration into ILD layers 23A and 23B. Copper is deposited by one of the known techniques, such as CVD, PVD electroplating or electroless plating. If electroplating is used, a thin copper seed layer 32 should be deposited above the diffusion layer 30 as a prerequisite for electroplating. Thus, depending on the deposition process, a so-obtained uppermost copper layer 34 has certain topography.
When manufacturing the aluminum-based structure 1 (FIG. 1), the application of a CMP process to the uppermost aluminum layer 12 is usually not needed. As for the copper-based structure 20 (or tungsten-based structure as well), the manufacturing process requires the use of metal removal. This is true also for processes where aluminum is deposited by the dual Damascene process.
Copper has properties that add to the polishing difficulties. Unlike tungsten, it is a soft metal and subject to scratching and embedding particles during polishing. Additionally, owing to the fact that copper is highly electrochemically active and does not form a natural protective oxide, it corrodes easily.
With the conventional technology of planarization, ILD polishing occurs after every metal deposition and etch step. The same is not true for damascene processing, wherein the post-polish surface is expected to be free of topography. However, topography is induced because of the erosion of densely packed small features arrays and dishing of the metal surface in large features.
Copper CMP is more complex because of the need completely to remove the tantalum or tantalum nitride barrier layers and copper without the overpolishing of any feature. This is difficult because current copper deposition processes are not as uniform as the oxide deposition process.
The effects of residues, dishing and erosion present defects on the wafer induced by the CMP process applied thereto. Dishing and erosion may deteriorate the interconnections"" quality, especially when the copper thickness is reduced. Indeed, the reduction of the copper thickness results in the increase of RC constants, resulting in the slower functioning of the integrated circuit. As indicated above, the lower resistance is critically important in high-performance microprocessors and fast static RAMs.
One of the possible solutions for minimizing the dishing and erosion consists of a tight control of the CMP process. This may, for example, be implemented by means of a compensation strategy using metal fills and dummy structures. However, this is a costly solution in terms of lost silicon for integrated circuits and added process and design complexity. It would be ideal to polish inlaid structures without the aid of such a process and design steps.
U.S. Pat. No. 5,872,633 discloses a method and apparatus for detecting the removal of thin film layers during the planarization. Although a technique presented in this patent is aimed at solving the residues related problem, it is capable of detecting an average thickness of a wafer under planarization, by eliminating information introduced by a pattern. It is thus evident that this technique does not provide precise measurements of the wafer""s parameters, and cannot be used for determining the erosion and dishing conditions at all, which conditions, if any, are observed in the pattern area.
There is accordingly a need in the art to facilitate a CMP process applied to patterned structures such as wafers having metal (e.g., copper) regions, by providing a novel method and system for monitoring the CMP process applied to such structures.
It is a major feature of the present invention to provide such a method which is capable of controlling the CMP process to prevent residues, dishing and erosion effects.
It is a further feature of the present invention to provide such a system which is capable of being integrated with the CMP process applied to wafers progressing along the production line.
The main idea of the present invention is based on the following. An optical monitoring system capable of thickness measurements in patterned structures is applied to selected locations (dies) on an article (wafer) and to predetermined sites within at least some of the selected locations. These predetermined sites are those of potential detrimental effects (i.e., residues, erosion and dishing).
To determine these sites, various methods can be used, based on simulations utilizing the information regarding the wafer""s structure and materials, which information is provided by a specific manufacturer, and/or based on a preliminary optical inspection of the wafer. These sites, when having at least some of the detrimental effects of the kind specified above, are characterized by optical properties different from xe2x80x9cnormalxe2x80x9d locations (i.e., free of the detrimental effects).
Having selected the sites of the potential detrimental effects, the optical monitoring system performs accurate thickness measurements, from which parameters (thicknesses) characterizing residues, erosion and dishing effects are derived. The optical system is capable of detecting light components reflected from the site under measurement and producing measured data. Analysis of this measured data utilizes an optical model based on some known features of the wafer""s structure and optical factors for producing theoretical data, and includes a fitting procedure of the measured and theoretical data to optimize the model and to calculate the thickness.
There is thus provided according to one aspect of the present invention a method for optical control of the quality of a CMP process applied to an article for determining at least one of residues, erosion and dishing conditions on said article, wherein the article has a patterned area containing a plurality of spaced-apart stacks each formed by a plurality of different layers and thereby defining a pattern in the form of spaced-apart metal regions, the method comprising the steps of:
(a) selecting at least one predetermined site on the article to be controlled;
(b) illuminating said at least one predetermined site;
(c) detecting spectral characteristics of light components reflected from the at least one illuminated site of the article, and generating data representative thereof; and
(d) analyzing said data for determining at least one parameter of the article within said at least one illuminated site.
The at least one site to be selected may be disposed outside the patterned area. In this case, the determined parameter is indicative of the existence of residues of materials to be removed from the article.
Preferably, the at least one predetermined site is selected in the following manner. A preliminary optical inspection is applied to the article to detect light reflected therefrom and to obtain data representative of the detected light. This data is then analyzed to detect sites having optical properties different from other locations on the article. These different optical properties may be defined by a certain range of contrast of the reflected light, or certain spectral characteristics of the reflected light. The existence of a pattern having substantially irregular geometry may be indicative of residues.
Preferably, at least two spatially separated sites of the article are illuminated, and data representative of light reflected from these sites are generated. These data are indicative of spectral characteristics of light components reflected from the illuminated sites. By analyzing the generated data, the parameters of the article within the illuminated sites can be determined. The determined parameters are the thicknesses of the article within these two sites.
If one of these sites is selected outside the patterned area, and the other site is selected inside the patterned area of the article, the difference between the thicknesses can be indicative of erosion within the site inside the patterned area. If both locations are located inside the patterned area, the difference between the thicknesses may be indicative of pattern dependent dishing and/or erosion condition.
More specifically, the present invention is used for monitoring a CMP process applied to wafers containing copper regions, and is therefore described below with respect to this application.